Created: May 17, 2015
Updated: May 26, 2015
SVN Updated: Jun 1, 2015
Other project properties
Development status: Stable
Additional info: Design done , FPGA proven , Specification done
WishBone Compliant: No
The FT245R is a USB to parallel FIFO interface with a very simple protocol (for both FPGA and software). FT245R interface core is intended to simplify the communication of your design with FT245R external chip. It takes care of delays and synchronization with the actual device. I tried to keep the core as simple as possible, however, although it is fully functional, there may be a place for further improvements, hence the status is "stable" rather than "done".
- Easy to use.
- Fast (the bandwidth mostly depends on client software implementation).
- Fully conforming the FT245R USB FIFO I.C. datasheet.
As it has been stated above, the module is designed with simplicity in mind resulting in a few control signals and three data ports (bidirectional port goes to FT245R and two uni-directional ports are used on "client side" for input/output).
|nrd||FT245R RD# pin.|
|nwr||FT245R WR pin.|
|ntxe||FT245R TXE# pin.|
|nrxf||FT245R RXF# pin.|
|nrst||FT245R RESET# pin.|
|data_io||FT245R FIFO data bus.|
|nce||Enables the FT245R interface component (active low).|
|reset||Resets the component.|
|data_in||Input data to be written to FIFO.|
|data_out||Outputs data read from FIFO.|
|busy||When high indicates that the component is either processing the last comand or is not enabled.|
|data_available||When high indicates that data is available for reading at data_out port.|
When strobed high (suggested not to hold high for more than one clock cycle) instructs the component to discard current data
(if such exists) and read a new byte from FIFO.
When strobed high (suggested not to hold high for more than one clock cycle) instructs the component to write a byte
from data_in port to the FIFO.
It is important to mention, that the component attempts to read the first byte automatically once nrxf and nce are low, meaning that the component is enabled
and data is available for reading from FIFO. All subsequent reads require strobing fetch_next_byte .
The following waveforms illustrate how data is read from the actual device.
The component ignores all fetch_next_byte and do_write signals when busy is high.
Below the waveforms of do_write
This is it. Please post any questions and/or suggestions via bugtrecker.