Created: May 31, 2013
Updated: Jul 3, 2013
SVN Updated: Aug 17, 2013
Other project properties
Development status: Alpha
Additional info: ASIC proven , Design done , FPGA proven , Specification done
WishBone Compliant: No
This core takes unsigned value as degrees(input) and gives the corresponding value in IEEE-754 double (output).
This core can be easily configured degrees(inputs) bit width can be changed to any number of bits.
It only takes 10 clock cycles to complete one operation.