Created: Apr 3, 2013
Updated: Jan 14, 2015
SVN Updated: Apr 5, 2013
Other project properties
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: No
This IP core provides resource efficient ternary adders, i.e., adders with three inputs performing s = x + y + z, for the Altera and Xilinx platforms.
Resource efficient means that they need exactly the same resources on modern FPGAs as two-input adders, but are slightly slower.
A complete description can be found in the ternary adder documentation: http://opencores.org/usercontent,doc,1365162582
Note that the used method for the Xilinx ternary is patented (US patent no 7,274,211). Hence, only private, research or non-commercial use is allowed with this implementation!