Created: Nov 5, 2010
Updated: Feb 26, 2011
SVN Updated: Apr 8, 2011
Other project properties
Development status: Beta
Additional info: Design done , Specification done
WishBone Compliant: No
Sine and cosine table that can be synthesized. Pure VHDL, no other tools or
silicon vendor macros. Pipeline delay can be selected from combinatorial
to 10 stages at compile time via a generic.
Phase input and sin/cos output widths are automatically determined by the
connected bus. 16 bit phase/18 bit amplitude runs at 230 MHz in Spartan6-3
without any optimization efforts. (Just setting 250 MHz as the goal)
Also features a programmable pipeline register entity for most basic VHDL types.
Pipeline delay can be set from 0 to MAXINT clocks
Also a library for conversion between reals and integer/fractional signed and unsigned.
The test bed can log the generated sinewaves to a file for inspection with matlab.