Created: Oct 29, 2002
Updated: Sep 30, 2010
SVN Updated: Mar 10, 2009
Other project properties
Development status: Stable
WishBone Compliant: No
This is synthesizeable radix 4 complex fft processor. Input data width and points are configurable. Output data width = Input data width + 2. Some necessary limited and shift have been done at every butterfly.
A sample implementation of a 1024 point 12 bit FFT runs at about 97MHz in a Spartan2e100 -6 device and occupies 1,271 LUTs (about 52%) and 1,144 registers (about 47%) of the device.
- Data width configurable
- Point configurable
- Input data during data output
- Simulation result has compare with Matlab result
- Design is available in VHDL from OpenCores CVS via cvsweb or via cvsget