Created: Oct 10, 2009
Updated: Jan 28, 2011
SVN Updated: Aug 3, 2010
Other project properties
Development status: Stable
Additional info: Design done
WishBone Compliant: No
A fast (single-cycle) base-2 log function, based on the description at
Need an electronic design solution? Visit http://www.cantares.on.ca/
First uploaded version is in Verilog, with pipelining to maximize the clock frequency. An example implementation: It takes less than 2% of the smallest CycloneIII, and runs at 250MHz on the IOs. Probably even higher if internal-only. It even fits in a mid-sized CPLD!
Second version strips outs the pipelining registers. Simpler if you don't need the throughput. This one clocks in at 14ns propagation delay pin-pin on the same CycloneIII. Not a bad speed for a logarithm, right? :-) (BTW, the syntax here requires System Verilog)
The third version is similar to the first, except the fractional LUT has been expanded for higher accuracy and resolution.
If you use any of these, please write and tell me about it!
p.s., check out my antilog project too - combine them for square-root