Created: Oct 28, 2002
Updated: Sep 28, 2011
SVN Updated: May 5, 2009
Other project properties
Development status: Stable
WishBone Compliant: No
This is a collection of synthesizeable hardware dividers. Different types of dividers are available. All dividers are fully pipelined and provide a 2N by N division every clock cycle. All designs are fully parameteriseable and synthesizeable.
The dividers take two inputs Z(2N-bit divident) and D(N-bit divisor), and return Q(N-bit quotient), S(N-bit remainder), div0(division by zero), and ovf(overflow).
A sample implementation of a 32/16 bit divider with a remainder output runs at about 82MHz in a Spartan2e100 -6 device and occupies 1132 LUTs (about 47%) and 1736 registers (about 72%) of the device.
- Fully synthesiseable
- Fully parameteriseable
- Pipelined design (one pipeline stage per bit) provides a result every clock cycle.
- Includes testbench
The following division units are ready and available for download:
- Non-restoring unsigned by unsiged divider
- Non-restoring signed by unsiged divider