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Source code

Details

Name: ecpu_alu
Created: Mar 24, 2009
Updated: Dec 20, 2009
SVN Updated: Apr 30, 2009

Other project properties

Category: Arithmetic core
Language: Verilog
Development status: Beta
Additional info: Design done
WishBone Compliant: No
License: GPL

Comments

# ECPU 0.1.alpha
# ==============
#
# Background
# ========
# Resurrected university project originally written in VHDL.
# Converted to Verilog by hand and fixed bugs.
#
# Modifications made in verilog post-conversion:
# - New barrel shifter
# - Reviewed opcode list
# - Enhanced testbench to allow for random stimulus (verilog only tb)
# - Tested using Icarus
#
# Currently checking for synthesis:
# - Passes synthesis checks using "veriwell ... +synopsys"
#
# Features
# ========
# * 15 working opcodes/functions :
# cADD_AB
# cINC_A
# cINC_B
# cSUB_AB
# cCMP_AB - Same as Xor
# cASL_AbyB - Uses last three bits of B (barrel shift)
# cASR_AbyB - Uses last three bits of B (barrel shift)
# cCLR - Clear outputs
# cDEC_A
# cDEC_B
# cMUL_AB - not implemented [yet]
# cCPL_A
# cAND_AB
# cOR_AB
# cXOR_AB
# cCPL_B
#
# * Flags C, V, Z - not implemented [yet]