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Source code

Details

Name: verilog_cordic_core
Created: Sep 14, 2008
Updated: Aug 12, 2011
SVN Updated: Mar 10, 2009

Other project properties

Category: Arithmetic core
Language: Verilog
Development status:
Additional info: Design done , FPGA proven
WishBone Compliant: No
License:

Description

A 100% behavioral implementation of a cordic core. The core is highly configurable through `defines. A testbench is included. See the included manual for details. Source and user manual available here

Status

- Tested in hardware